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| INTEGRATED CIRCUITS DATA SHEET TDA9874H Digital TV sound demodulator/decoder Preliminary specification File under Integrated Circuits, IC02 1998 Apr 27 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder CONTENTS 1 2 2.1 3 4 5 5.1 5.2 6 6.1 6.2 6.3 7 7.1 7.2 7.3 7.4 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 FEATURES GENERAL DESCRIPTION Supported standards ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION Description of the demodulator and decoder section Description of the DSP Description of the analog audio section I2C-BUS CONTROL Introduction Power-up state Slave receiver mode Slave transmitter mode I2S-BUS DESCRIPTION EXTERNAL COMPONENTS LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS TDA9874H 1998 Apr 27 2 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 1 FEATURES TDA9874H * SIF input switch e.g. to select between terrestrial TV SIF and SAT SIF sources * SIF AGC with 21 dB control range * SIF 8-bit Analog-to-Digital Converter (ADC) * DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation * NICAM decoding (B/G, I and L standard) * Two-carrier multi-standard FM demodulation (B/G, D/K and M standard) * Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound * Adaptive de-emphasis for satellite * Programmable identification (B/G, D/K and M standard) and different identification times * Optional AM demodulation for system L, simultaneously with NICAM * Monitor selection for FM/AM demodulator outputs and FM and NICAM signals * Digital crossbar switch * I2S serial audio output with matrix, level adjust and mute * Dual audio Digital-to-Analog Converter (DAC) from digital crossbar switch to analog crossbar switch, bandwidth 15 kHz * Analog crossbar switch with inputs for mono and stereo * Output selection of mono, stereo, dual, dual A or dual B * 20 kHz bandwidth for analog path * Standby mode. 2 GENERAL DESCRIPTION 2.1 Supported standards The multi-standard/multi-stereo capability of the TDA9874H is mainly of interest in Europe, but also in Hong Kong/PR China and South East Asia. This includes B/G, D/K, I, M and L standard. In other application areas there exist subsets of those standard combinations or only single standards are transmitted. Standard M is transmitted in Europe by the American Forces Network with European channel spacing (7 MHz VHF, 8 MHz UHF) and monaural sound. The AM sound of L/L' standard is normally demodulated in the 1st sound IF. The resulting AF signal has to be entered into the mono audio input of the TDA9874H. A second possibility is to use the internal AM demodulator stage, giving limited performance. Korea has a stereo sound system similar to Europe and is supported by the TDA9874H. Differences include deviation, modulation contents and identification. It is based on M standard. An overview of the supported standards and sound systems and their key parameters is given in Table 1. The analog multi-channel systems are sometimes also named 2CS (2 carrier systems). The TDA9874H is a single-chip Digital TV Sound Demodulator/Decoder (DTVSD1) for analog and digital multi-channel sound systems in TV/VCR sets and satellite receivers. 1998 Apr 27 3 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 2.1.1 Table 1 ANALOG 2-CARRIER SYSTEMS Frequency modulation SOUND SYSTEM mono A2+ A2 mono A2 A2* CARRIER FREQUENCY (MHz) 4.5 4.5/4.724 5.5/5.742 6.0 6.5/6.742 6.5/6.258 FM DEVIATION (kHz) NOM. 15 15 27 27 27 27 MAX. 25 25 50 50 50 50 OVER. 50 50 80 80 80 80 1 1 1 1 TDA9874H MODULATION SC1 mono 2(L STANDARD M M B/G I D/K D/K Table 2 SC2 - 1 (L 2 BANDWIDTH/ DE-EMPHASIS (kHz/s) 15/75 15/75 (Korea) 15/50 15/50 15/50 15/50 + R) - R) 2(L + R) R - R R mono 2(L + R) 2(L + R) Identification for A2 systems PARAMETER A2; A2* 54.6875 kHz = 3.5 x line frequency line frequency 117.5 Hz = -----------------------------------133 line frequency 274.1 Hz = -----------------------------------57 50% A2+ (KOREA) 55.0699 kHz = 3.5 x line frequency line frequency 149.9 Hz = -----------------------------------105 line frequency 276.0 Hz = -----------------------------------57 50% Pilot frequency Stereo identification frequency Dual identification frequency AM modulation depth 2.1.2 Table 3 2-CARRIER SYSTEMS WITH NICAM NICAM SC1 MODULATION SC2 ROLL-OFF NICAM (MHz) DE-EMPHASIS (%) CODING NICAM STANDARD FREQUENCY TYPE (MHz) INDEX (%) DEVIATION (kHz) NOM. MAX. NOM. MAX. B/G I D/K L Note 1. See "EBU specification" or equivalent specification. 5.5 6.0 6.5 6.5 FM FM FM AM - - - 54 - - - 100 27 27 27 - 50 50 50 - 5.85 6.552 5.85 5.85 J17 J17 J17 J17 40 100 40 40 note 1 note 1 tbf note 1 1998 Apr 27 4 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 2.1.3 SATELLITE SYSTEMS TDA9874H An important specification for satellite TV reception is the Astra specification. The TDA9874H is suited for the reception of Astra and other satellite signals, with sound carrier frequencies from 4 to 9.2 MHz. Table 4 FM satellite sound CARRIER FREQUENCY (MHz) 6.50(1) 7.02/7.20 7.38/7.56 7.74/7.92 8.10/8.28 MODULATION INDEX 0.26 0.15 0.15 0.15 0.15 MAXIMUM FM DEVIATION (kHz) 85 50 50 50 50 MODULATION mono m/st/d(2) m/st/d(2) m/st/d(2) m/st/d(2) BANDWIDTH/ DE-EMPHASIS (kHz/s) 15/50(1) 15/adaptive(3) 15/adaptive(3) 15/adaptive(3) 15/adaptive(3) CARRIER TYPE Main Sub Sub Sub Sub Notes 1. For other satellite systems, frequencies of e.g. 5.80 MHz, 6.60 MHz or 6.65 MHz can also be received. A de-emphasis of 60 s or in accordance with J17 is available. 2. m/st/d = mono or stereo or dual language sound. 3. Adaptive de-emphasis = compatible to transmitter specification. 3 ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION SOT205-1 TDA9874H QFP44 plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm 1998 Apr 27 5 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 4 BLOCK DIAGRAM TDA9874H handbook, full pagewidth SIF2 37 42 13 19 29 30 23 I2C-BUS INTERFACE INPUT SWITCH AGC, ADC SIF1 25 21 20 24 18 VDDA2 VSSA2 Vref1 Iref P1 P2 ADDR1 ADDR2 SCL SDA SUPPLY SIF IDENTIFICATION FM/AM DEMODULATION NICAM DEMODULATION TIMING DETECTION DAC 14 10 12 6 5 8 7 28 27 35 36 26 3 4 41 Vtune NICAM PCLK VDDD1 VSSD1 VDDD2 VSSD2 VDDD3 VSSD3 VDDD4 VSSD4 CRESET VDDA1 VSSA1 Vref2 VDDA3 VSSA3 EXTIR EXTIL MONOIN XTALI XTALO SYSCLK 15 16 34 VCXO CLOCK DEMATRIX NICAM DECODER DIGITAL SUPPLY LEVEL ADJUST 2 CHANNEL ANALOG/ SATELLITE DECODER SUPPLY DAC SDO WS SCK 31 32 33 I2S-BUS INTERFACE DIGITAL SELECTOR POSTFILTER 2 DACS REFERENCE SUPPLY OPERATIONAL AMPLIFIERS 43 44 39 40 38 TDA9874H ANALOG CROSSBAR SWITCH TEST1 TEST2 TP1 TP2 22 17 11 9 TEST AF-OUPUT BUFFERS 2 OUTR 1 OUTL MGL248 Fig.1 Block diagram. 1998 Apr 27 6 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 5 5.1 PINNING INFORMATION Pinning TDA9874H 38 MONOIN 35 VDDD4 36 VSSD4 43 VDDA3 44 VSSA3 handbook, full pagewidth 34 SYSCLK 39 EXTIR 40 EXTIL 41 Vref2 42 P2 37 P1 OUTL 1 OUTR 2 VDDA1 3 VSSA1 4 VSSD1 5 VDDD1 6 VSSD2 7 VDDD2 8 TP2 9 NICAM 10 TP1 11 33 SCK 32 WS 31 SDO 30 SDA 29 SCL TDA9874H 28 VDDD3 27 VSSD3 26 CRESET 25 SIF1 24 Vref1 23 SIF2 VDDA2 21 ADDR1 13 XTALO 16 TEST2 17 ADDR2 19 VSSA2 20 TEST1 22 PCLK 12 Vtune 14 XTALI 15 Iref 18 MGK752 Fig.2 Pin configuration. 1998 Apr 27 7 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 5.2 Pin description SOT205-1 package PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 analog output left analog output right analog supply voltage 1; DAC circuitry analog ground supply 1; DAC circuitry digital ground supply 1; DAC circuitry digital supply voltage 1; DAC circuitry digital ground supply 2; DSP part digital supply voltage 2; DSP part additional test pin 2; connected to VSSD for normal operation serial NICAM data output at 728 kHz additional test pin 1; connected to VSSD for normal operation NICAM clock output at 728 kHz first I2C-bus slave address modifier tuning voltage output for crystal oscillator crystal oscillator input crystal oscillator output test pin 2; connected to VSSD for normal operation resistor for reference current generation; front end circuitry second I2C-bus slave address modifier analog ground supply 2; analog front end circuitry analog supply voltage 2; analog front end circuitry test pin 1; connected to VSSD for normal operation sound IF input 2 reference voltage; analog front end circuitry sound IF input 1 capacitor for power-on reset digital ground supply 3; front end circuitry digital supply voltage 3; front end circuitry I2C-bus clock input I2C-bus data input/output I2S-bus serial data output DESCRIPTION TDA9874H Table 5 SYMBOL OUTL OUTR VDDA1 VSSA1 VSSD1 VDDD1 VSSD2 VDDD2 TP2 NICAM TP1 PCLK ADDR1 Vtune XTALI XTALO TEST2 Iref ADDR2 VSSA2 VDDA2 TEST1 SIF2 Vref1 SIF1 CRESET VSSD3 VDDD3 SCL SDA SDO 1998 Apr 27 8 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder TDA9874H SYMBOL WS SCK SYSCLK VDDD4 VSSD4 P1 MONOIN EXTIR EXTIL Vref2 P2 VDDA3 VSSA3 PIN 32 33 34 35 36 37 38 39 40 41 42 43 44 I2S-bus I2S-bus word select input/output clock input/output DESCRIPTION system clock output digital supply voltage 4; demodulator circuitry digital ground supply 4; demodulator circuitry first general purpose I/O pin analog mono input external audio input right channel external audio input left channel analog reference voltage DAC and operational amplifiers second general purpose I/O pin analog supply voltage 3; operational amplifiers analog ground supply 3; operational amplifiers 1998 Apr 27 9 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 6 6.1 6.1.1 FUNCTIONAL DESCRIPTION Description of the demodulator and decoder section SIF INPUT 6.1.6 FM IDENTIFICATION TDA9874H Two input pins are provided. SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tuner. As no specific filters are integrated, both inputs have the same specification giving flexibility in application. The selected signal is passed through an AGC and then digitized by an 8-bit ADC running at 24.576 MHz. 6.1.2 AGC The identification of the FM sound mode is performed by AM synchronous demodulation of the pilot and narrow-band detection of the identification frequencies. The result is available via the I2C-bus interface. A selection can be made via the I2C-bus for B/G, D/K and M standard, and for three different time constants that represent different trade-offs between speed and reliability of identification. 6.1.7 NICAM DEMODULATION The gain of the AGC amplifier is controlled from the ADC output by means of a digital control loop employing hysteresis. The AGC has a fast attack behaviour to prevent ADC overloads, and a slow decay behaviour to prevent AGC oscillations. For AM demodulation the AGC must be switched off. When switched off, the control loop is reset and fixed gain settings can be chosen from a table. The AGC can be controlled via the I2C-bus. Details can be found in Sections 7.3.1, 7.3.2 and 7.4.6. 6.1.3 MIXER The NICAM signal is transmitted in a DQPSK code at a bit rate of 728 kbits/s. The NICAM demodulator performs DQPSK demodulation and passes the resulting bitstream and clock signal to the NICAM decoder and, for evaluation purposes, to pins. A timing loop controls the frequency of the crystal oscillator to lock the sampling instants to the symbol timing of the NICAM data. The polarity of the control signal is selectable to support applications, in which external circuitry is used to boost the tuning voltage of the oscillator. 6.1.8 NICAM DECODING The digitized input signal is passed on to the mixers, which mix one or both input sound carriers down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access to the mixer control word registers is via the I2C-bus (see Sections 7.3.4 and 7.3.5). When receiving NICAM programs, a feedback signal is added to the control word of the second carrier mixer to establish a carrier-frequency loop. 6.1.4 FM AND AM DEMODULATION The device performs all decoding functions in accordance with the "EBU NICAM 728 specification". After locking to the frame alignment word, the data are descrambled by application of the defined pseudo-random binary sequence, and the device synchronizes to the periodic frame flag bit C0. The status of the NICAM decoder can be read-out from the NICAM Status Register by the user (see Section 7.4.2). The OSB bit indicates that the decoder has locked to the NICAM data. The VDSP bit indicates that the decoder has locked to the NICAM data and that the data is valid sound data. The C4 bit indicates that the sound conveyed by the FM mono channel is identical to the sound conveyed by the NICAM channel. The error byte contains the number of sound sample errors, resulting from parity checking, that occurred in the past 128 ms period. The Bit Error Rate (BER) is approximately 0.0000174 times the contents of the error byte. -5 bit errors BER = ---------------------- error byte x 1.74 x 10 total bits An FM or AM input signal is passed through a band-limiting filter onto a demodulator that can be used for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis is available for Wegener-Panda 1 encoded satellite programs. 6.1.5 FM DECODING A two-carrier stereo decoder recovers the left and right signal channels from the demodulated sound carriers. Both the European and Korean stereo systems are supported. 1998 Apr 27 10 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 6.1.9 NICAM AUTO-MUTE TDA9874H When the AM sound in NICAM L systems is demodulated in the 1st sound IF and the audio signal connected to the mono input of the TDA9874H, the controlling microprocessor has to take care of switching from NICAM reception to mono input, if auto-muting is desired. This could be achieved by setting the AMSEL bit HIGH additionally to AMUTE bit LOW (see also Section 7.3.11). 6.1.10 CRYSTAL OSCILLATOR This function is enabled by setting bit AMUTE LOW (see Section 7.3.11). Upper and lower error limits may be defined by writing appropriate values to two registers in the I2C-bus section (see Sections 7.3.13 and 7.3.14). When the number of errors in a 128 ms period exceeds the upper error limit, the auto-mute function will switch the output sound from NICAM to whatever sound is on the first sound carrier (FM or AM) or to the analog mono input. When the error count is smaller than the lower error limit, the NICAM sound is restored. The auto-mute function can be disabled by setting bit AMUTE HIGH. In this case clicks become audible, when the error count increases. The user will hear a signal of degrading quality. A decision to enable/disable the auto-muting is taken by the microprocessor based on an interpretation of the application control bits C1, C2, C3 and C4, and possibly any additional strategy implemented by the setmaker in the microcontroller software. A circuit diagram of the external components of the voltage-controlled crystal oscillator is shown in Fig.7 in Chapter 9. 6.1.11 TEST PINS All test pins are active HIGH. In normal operation of the device they can be left open-circuit, as they have internal pull-down resistors. Test functions are for manufacturing tests only and are not available to customers. 1998 Apr 27 11 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 6.2 6.2.1 Description of the DSP LEVEL SCALING 6.2.5 FM MONITOR TDA9874H All input channels to the digital crossbar switch are equipped with a level adjust facility to change the signal level in a range of 15 dB. Adjusting the signal level is intended to compensate for the different modulation parameters of the various TV standards. It is recommended to scale all input channels to be 15 dB below full-scale (-15 dB (FS)) under nominal conditions. This will create sufficient headroom to cope with overmodulation and avoids changes of the volume impression when switching from FM to NICAM or vice versa. 6.2.2 NICAM PATH This function provides data words from the FM demodulator outputs and FM and NICAM signals for external use, like carrier search or fine tuning. Source selection and data read-out are performed via the I2C-bus. 6.2.6 DIGITAL CROSSBAR SWITCH Input channels come from the FM and NICAM paths, while output channels comprise I2S and the audio DACs to the analog crossbar switch. Note that there is no connection from the external analog audio inputs to the digital crossbar switch. 6.2.7 DIGITAL AUDIO OUTPUT The NICAM path has a switchable J17 de-emphasis. 6.2.3 NICAM AUTO-MUTE If NICAM is received, the AUTO-MUTE is enabled and the signal quality becomes poor, the digital crossbar switches automatically to FM, Channel 1 or the analog mono input, as selected by bit AMSEL. This automatic switching depends on the NICAM bit error rate. The auto-mute function can be disabled via the I2C-bus. 6.2.4 FM (AM) PATH The digital audio output interface comprises an I2S output port and a system clock output. The I2S port is equipped with a level adjust facility that can change the signal level in a 15 dB range in 1 dB steps. Muting is possible, too, and outputs can be disabled to improve EMC performance. The I2S-bus output matrix provides the functions of forced mono, stereo, channel swap, Channel 1 or Channel 2. 6.2.8 CHANNEL TO THE ANALOG CROSSBAR PATH A high-pass filter suppresses DC offsets from the FM demodulator that may occur due to carrier frequency offsets and supplies the FM monitor function with DC values, e.g. for the purpose of microprocessor controlled carrier search or fine-tuning functions. An adaptive de-emphasis is available for Wegener-Panda 1 encoded satellite programs. The de-emphasis stage offers a choice of settings for the supported TV standards. The 2 channel decoder performs the dematrixing of 1 (L + R) and R to L and R signals, of 1 (L + R) and 2 2 1 (L - R) to L and R signals or of Channel 1 and 2 Channel 2 to L and R signals, as demanded by the different TV standards or user preferences. A level adjust function is provided with control positions 0 dB, +3 dB, +6 dB and +9 dB in combination with the audio DACs. 6.2.9 GENERAL The level adjust functions can provide signal gain at multiple locations. Great care has to be taken when using gain with large input signals, e.g., due to overmodulation, in order not to exceed the maximum possible signal swing, which would cause severe signal distortion. The nominal signal level of the various signal sources to the digital crossbar switch should be 15 dB below digital full-scale, i.e., -15 dB (FS). 1998 Apr 27 12 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Apr 27 NICAM FIXED DE-EMPHASIS LEVEL ADJUST DIGITAL CROSSBAR SELECT MATRIX LEVEL ADJUST I2S Philips Semiconductors handbook, full pagewidth Digital TV sound demodulator/decoder LEVEL ADJUST LEVEL ADJUST DAC 13 FM DC FILTER ADAPTIVE DE-EMPHASIS FIXED DE-EMPHASIS 2 CHANNEL DECODER FM MONITOR I2C MGK755 Preliminary specification TDA9874H Fig.3 DSP data flow diagram. Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 6.3 6.3.1 Description of the analog audio section ANALOG CROSSBAR SWITCH AND ANALOG MATRIX 6.3.2 EXTERNAL AND MONO INPUTS TDA9874H The TDA9874H has one external analog stereo input, one mono input and one two-channel output port. Analog source selector switches are employed to provide the desired analog signal routing capability, which is done by the analog crossbar switch section. The basic signal routing philosophy of the TDA9874H is that each switch handles two signal channels at the same time, e.g. Left and Right, language A and B, directly at the source. For an overview of the signal flow see Fig.5. Each source selector switch is followed by an analog matrix to perform further selection tasks, like putting a signal from one input channel, say, language A, to both output channels or for swapping left and right channel. The analog matrix provides the functions given in Table 6. All switches and matrices are controlled via the I2C-bus. Table 6 Analog matrix functions MATRIX OUTPUT MODE L OUTPUT 1 2 3 4 L input R input L input R input R OUTPUT R input L input L input R input The external and mono inputs accept signal levels of up to 1.4 V (RMS). By adding external series resistors to provide a suitable attenuation, the external input could be used as a SCART input. Whenever the external or mono input is selected, the output of the DAC is muted to improve the crosstalk performance. 6.3.3 DUAL AUDIO DAC The TDA9874H comprises a two-channel audio DAC for feeding signals from the DSP section to the analog crossbar switch. These DACs have a resolution of 15 bits and employ four-fold oversampling and noise shaping. 6.3.4 AUDIO OUTPUT BUFFERS The output buffers provide 0 dB of gain and offer a muting possibility. The post filter capacitors of the audio DACs are connected to the buffer outputs. 6.3.5 STANDBY MODE The Standby mode (see Section 7.3.2) disables most functions and reduces power dissipation of the TDA9874H, but provides no other functionality. Internal registers may lose their information in Standby mode. Therefore, the device needs to be initialized on returning to normal operation. This can be accomplished in the same way as after a power-on reset. handbook, full pagewidth source select mono (AM) EXTIL EXTIR matrix OUTL DACL DACR OUTR MGK754 Fig.4 Switch diagram for the audio section. 1998 Apr 27 14 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Apr 27 mono ANALOG CROSSBAR SWITCH NICAM DEMODULATOR NICAM DECODER DE-EMPHASIS LEVEL ADJUST DIGITAL CROSSBAR SELECT FM/AM FM/AM DEMODULATOR ADAPTIVE DE-EMPHASIS FIXED DE-EMPHASIS 2 CHANNEL DECODER LEVEL ADJUST MATRIX LEVEL ADJUST I2S LEVEL ADJUST DAC MATRIX external NICAM Philips Semiconductors handbook, full pagewidth Digital TV sound demodulator/decoder BUFFER OUT 15 MGK756 Preliminary specification TDA9874H Fig.5 Audio signal flow. Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7 7.1 I2C-BUS CONTROL Introduction 7.2 Power-up state TDA9874H At power-up the device is in the following state: * All outputs muted * No sound carrier frequency loaded * General purpose I/O pins ready for input (HIGH) * Input SIF1 selected with: - AGC on - Small hysteresis. * Demodulators for both sound carriers set to FM with: - Identification for B/G, D/K, identification mode `slow' - Level adjust set to 0 dB - De-emphasis 50 s - Dematrix set to mono - Adaptive de-emphasis on. * OUTL and OUTR set to mono and connected to DAC * Digital audio interface all outputs off * Monitor set to carrier 1 DC output. 0 1 0 1 After power-up a device initialization has to be performed via the I2C-bus to put the TDA9874H into the proper mode of operation, in accordance with the desired TV standard, etc. This can be done by writing to all registers with a single I2C-bus transmission (like a refresh operation) or by writing selectively only to those registers, the contents of which need to be changed with regard to the power-up state. The TDA9874H is controlled only via the I2C-bus. Control is exercised by writing data to one or more internal registers. Status information can be read from an array of registers to let the controlling microprocessor determine whether any action is required. The device has an I2C-bus slave transceiver in accordance with the fast-mode specification with a maximum speed of 400 kbits/s. Information about the I2C-bus can be found in brochure "I2C-bus and how to use it" (order number 9398 393 40011). To avoid conflicts in a real application with other ICs providing similar or complementing functions, there are four possible slave addresses available, which can be selected by pins ADDR1 and ADDR2 (see Table 7). Table 7 ADDR2 0 0 1 1 Possible slave addresses SLAVE ADDRESS ADDR1 A6 A5 A4 A3 A2 A1 A0 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 The I2C-bus interface remains operational in the Standby mode of the TDA9874H to allow the device to be reactivated via the I2C-bus. The device will not respond to a `general call' on the I2C-bus, i.e. when a slave address of 0000000 is sent by a master. 1998 Apr 27 16 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3 Slave receiver mode TDA9874H As a slave receiver, the TDA9874H provides 24 registers for storing commands and data. Each register is accessed via a so-called subaddress. A subaddress can be thought of as a pointer to an internal memory location. Detailed descriptions of the slave receiver registers are given in Sections 7.3.1 to 7.3.20. Table 8 S Table 9 I2C-bus; SLAVE ADDRESS/SUBADDRESS/DATA format SLAVE ADDRESS Explanation of Table 8 BIT S SLAVE ADDRESS 0 A SUBADDRESS DATA A/NA P START condition 7-bit device address data direction bit (write to device) acknowledge address of register to write to data byte to be written into register acknowledge or not acknowledge STOP condition FUNCTION 0 A SUBADDRESS A DATA A/NA P It is allowed to send more than one data byte per transmission to the TDA9874H. In that case, the subaddress is automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte that is properly stored, is acknowledged with A (acknowledge). If an attempt is made to write data to a non-existing subaddress, the device acknowledges with NA (not acknowledge), therefore telling the I2C-bus master to abort the transmission. There is no `wrap-around' of subaddresses. Commands and data will be processed as soon as they have been received completely. Functions requiring more than one byte will, thus, be executed only after all bytes for that function have been received. If the transmission is terminated (STOP condition) before all bytes have been received, the incomplete data for that function are ignored. Table 10 Format for a transmission employing auto-increment of subaddresses S SLAVE ADDRESS 0 A SUBADDRESS A DATA BYTE A n data bytes with auto-increment of subaddresses DATA A/NA P Data patterns sent to the various subaddresses are not checked for being illegal or not at that address, except for the level adjust functions. Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. In this case, the last operation will not be executed. 1998 Apr 27 17 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Apr 27 18 Philips Semiconductors Table 11 Overview of the slave receiver registers Digital TV sound demodulator/decoder SUBADDRESS (DECIMAL) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DATA FUNCTION 7 B7 P2OUT - B7 B7 B7 B7 B7 B7 IDMOD1 - B7 B7 - B7 B7 B7 1 DGS1 - - - B7 6 B6 P1OUT - B6 B6 B6 B6 B6 B5 IDMOD0 - B6 B6 - B6 B6 B6 MUTI2S - CSM2 - ICSM2 B6 5 B5 STDBY - B5 B5 B5 B5 B5 B5 IDAREA - B5 B5 TIMPOL B5 B5 B5 1 - CSM1 - ICSM1 B5 4 B4 INIT MCSM1 B4 B4 B4 B4 B4 B4 - - B4 B4 DOUTEN B4 B4 B4 1 - CSM0 SYSCL1 ICSM0 B4 3 B3 0 MCSM0 B3 B3 B3 B3 B3 B3 ADEEM1 - B3 B3 - B3 B3 B3 1 DGS0 - SYSCL0 - B3 2 B2 AGCSLOW - B2 B2 B2 B2 B2 B2 FMDSC13 FDMS2 B2 B2 AMSEL B2 B2 B2 MUTOUT - - SYSOUT - B2 1 B1 AGCOFF MSS1 B1 B1 B1 B1 B1 B1 0 B0 SIFSEL MSS0 B0 B0 B0 B0 B0 B0 AGC gain selection (ignored, if AGC on) general configuration monitor select carrier 1 frequency; MS part carrier 1 frequency carrier 1 frequency; LS part carrier 2 frequency; MS part carrier 2 frequency carrier 2 frequency; LS part CH2MOD1 CH2MOD0 CH1WIDE CH1MODE demodulator configuration FMDSC12 FMDSC11 FM de-emphasis FDMS1 B1 B1 NDEEM B1 B1 B1 1 DOS1 SS1 I2SFORM ISS1 B1 FDMS0 B0 B0 AMUTE B0 B0 B0 1 DOS0 SS0 IS2OUT ISS0 B0 FM dematrix Channel 1 output level adjust Channel 2 output level adjust NICAM configuration NICAM output level adjust NICAM lower error limit NICAM upper error limit audio mute control DAC output select analog output select digital audio interface configuration I2S output select I2S output level adjust ADEEM2 FMDSC23 FMDSC22 FMDSC21 Preliminary specification TDA9874H Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.1 AGC GAIN REGISTER (AGCGR) TDA9874H If the Automatic Gain Control (AGC) function is switched off in the General Configuration Register (see Section 7.3.2), the contents of this register defines a fixed gain of the SIF input stage. The input voltages given are meant to generate a nearly full-scale output from the SIF ADC. If the AGC is on, the contents of this register are ignored. The default setting at power-up is 00000000. In Table 12 the stated step number corresponds with the SIF level read from subaddress 7 (see Section 7.4.6); the input voltages should be considered as approximate target values. Table 12 AGC Gain Register (subaddress 0) 7 B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 2 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 STEP B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIF INPUT VOLTAGE (mV (RMS)) 240 214 195 176 159 145 131 119 107 99 90 82 76 70 65 60 55 51 48 45 42 39 36 34 32 30 29 27 25 24 23 22 1998 Apr 27 19 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.2 GENERAL CONFIGURATION REGISTER (GCONR) TDA9874H The default setting at power-up is 11000000. Table 13 General Configuration Register (subaddress 1) 7 P2OUT 6 P1OUT 5 STDBY 4 INIT 3 - 2 AGCSLOW 1 AGCOFF 0 SIFSEL Table 14 Description of GCONR bits BIT 7 6 SYMBOL P2OUT P1OUT DESCRIPTION General purpose I/O pins 1 and 2. These bits control general-purpose input/output pins. The contents of these bits is written directly to the corresponding pins. If an input is desired, the bits must be set HIGH to allow the pins to be pulled LOW externally. Input from the pins is reflected in the Device Status Register (see Section 7.4.1). P1OUT is recommended to be used for switching an SIF trap for the adjacent picture carrier in designs that employ such a trap. Standby mode on/off. STDBY = 1, puts the TDA9874H into the Standby mode. Most functions are disabled and power dissipation is somewhat reduced. STDBY = 0, the TDA9874H is in its normal mode of operation. On return from Standby mode, the device is in its Power-on reset mode and needs to be re-initialized with data defined by the setmaker. Initialize to default settings. INIT = 1, causes initialization of TDA9874H to its default settings. This has the same effect as a power-on reset. In case there is a conflict between the default settings and any bit set HIGH in this register, the bits of this register have priority over the corresponding default setting. This bit is automatically reset to LOW after initialization has completed. When set LOW, the TDA9874H is in its normal mode of operation. This bit is not used and should be set to a logic 0. AGC decay time. AGCSLOW = 1, a longer decay time and larger hysteresis are selected for input signals with strong video modulation (intercarrier). This bit has only an effect, when bit AGCOFF = 0. AGCSLOW = 0, selects normal attack and decay times for the AGC and a small hysteresis. Note. AGCSLOW bit should be set to HIGH for best possible audio performance. 1 AGCOFF AGC on/off. AGCOFF = 1, forces the AGC block to a fixed gain as defined in the AGC Gain Register (see Section 7.3.1). AGCOFF = 0, the automatic gain control function is enabled and the contents of the AGC gain register is ignored. SIF input select. SIFSEL = 1, selects pin SIF2 for input (recommended for satellite tuner). SIFSEL = 0, pin SIF1 (recommended for terrestrial TV) is selected. 5 STDBY 4 INIT 3 2 - AGCSLOW 0 SIFSEL 1998 Apr 27 20 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.3 MONITOR SELECT REGISTER (MSR) TDA9874H This register is used to define the signal source, the level of which is to be monitored, and the signal channel. Data can be monitored before or behind the DC filter at the FM/AM demodulator outputs. The last available data sample can be read-out in the I2C-bus slave transmitter mode (see Section 7.4.5). Phase means the differentiated phase output of the FM demodulator and is provided, when the demodulator operates in FM mode, while magnitude is supplied in AM mode. The default setting at power-up is 00000000. Table 15 Monitor Select Register (subaddress 2) 7 - 6 - 5 - 4 MCSM1 3 MCSM0 2 - 1 MSS1 0 MSS0 Table 16 Description of MSR bits BIT 7 6 5 4 3 2 1 0 SYMBOL - - - MCSM1 MCSM0 - MSS1 MSS0 Signal channel select. The state of these 2 bits determine which signal channel is selected; see Table 17. This bit is not used and should be set to logic 0. Signal source select. The state of these 2 bits determine which signal source is selected; see Table 18. DESCRIPTION These 3 bits are not used and should be set to logic 0. Table 17 Signal channel selection MCSM1 0 0 1 MCSM0 0 1 0 Channel 1 + Channel 2 -----------------------------------------------------------2 Channel 1 Channel 2 SIGNAL CHANNEL Table 18 Signal source selection MSS1 0 0 1 1 MSS0 0 1 0 1 DC output of FM/AM demodulator magnitude/phase output of FM/AM demodulator FM/AM path output NICAM path output SIGNAL SOURCE 1998 Apr 27 21 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.4 CARRIER 1 FREQUENCY REGISTER (C1FR) TDA9874H Three bytes are required to define a 24-bit frequency control word to represent the sound carrier (i.e. mixer) frequency. These three bytes are stored at subaddresses 3 to 5; subaddress 3 being the High byte. Execution of the command starts only after all bytes have been received. If an error occurs, e.g. a premature STOP condition, partial data for this function are ignored. The sound carrier frequency can be calculated in accordance with the following formula: f mix 24 data = -------- x 2 f clk with: data = 24-bit frequency control word fmix = desired sound carrier frequency fclk = 12.288 MHz (clock frequency of mixer) 224 = 16777216 (number of steps in a 24-bit word size). Example: A 5.5 MHz sound carrier frequency will be generated by sending the following sequence of data bytes to the TDA9874H (data = 7509333 in decimal notation or 729555 in hexadecimal notation): 01110010 10010101 01010101. The default setting at power-up is 00000000 for all three bytes. Table 19 Carrier 1 Frequency Register High byte (subaddress 3) 7 B7 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 Table 20 Carrier 1 Frequency Register Middle byte (subaddress 4) 7 B7 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 Table 21 Carrier 1 Frequency Register Low byte (subaddress 5) 7 B7 7.3.5 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 CARRIER 2 FREQUENCY REGISTER (C2FR) The format is the same as for sound carrier 1, except subaddresses 6 to 8 are used. Subaddress 6 holds the High byte. If the Carrier 2 Frequency Register is used, it will be for either the second FM sound carrier of a terrestrial or satellite FM program or the NICAM sound carrier. 7.3.5.1 Note While NICAM mode is used, the sound carrier 2 frequency should be set 2 kHz of the NICAM carrier frequency to improve carrier loop settling. For a deviation of +2 kHz this results in the following settings: Standard B/G, D/K and L: 5.850 MHz + 2 kHz = 5.852 MHz = (79EAAAH). Standard I: 6.552 MHz + 2 kHz = 6.554 MHz = (888AAAH). 1998 Apr 27 22 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.6 DEMODULATOR CONFIGURATION REGISTER (DCONR) TDA9874H The default setting at power-up is 00000000. Table 22 Demodulator Configuration Register (subaddress 9) 7 IDMOD1 6 IDMOD0 5 IDAREA 4 - 3 CH2MOD1 2 CH2MOD0 1 CH1WIDE 0 CH1MODE Table 23 Description of DCONR bits BIT 7 6 5 SYMBOL IDMOD1 IDMOD0 IDAREA DESCRIPTION Identification mode for FM sound. These bits define the integrator time of the FM identification. A valid result may be expected after twice this time has expired, at the latest. The longer the time, the more reliable the identification. See Table 24. Application area for FM identification. IDAREA = 1, selects FM identification frequencies in accordance with the specification for Korea. IDAREA = 0, frequencies for Europe are selected (B/G and D/K standard). This bit is not used and should be set to logic 0. Channel 2 receive mode. These bits control the hardware for the second sound carrier in accordance with Table 25. NICAM mode employs a wider bandwidth of the decimation filters than FM mode. Channel 1 bandwidth. CH1WIDE = 1, switches the decimation filters for the first sound carrier to a wide bandwidth, so that the main sound carrier of a satellite channel with its larger deviation can be handled without additional distortion. CH1WIDE = 0, the bandwidth is narrow to cope with the intermodulation requirements of FM stereo. Channel 1 receive mode. CH1MODE = 1, selects the hardware for the first sound carrier to operate in AM mode. CH1MODE = 0, FM mode is selected. This applies to both terrestrial and satellite FM reception. 4 3 2 1 - CH2MOD1 CH2MOD0 CH1WIDE 0 CH1MODE Table 24 Identification mode IDMOD1 0 0 1 1 IDMOD0 0 1 0 1 slow medium fast off/reset IDENTIFICATION MODE Table 25 Channel 2 receive mode CH2MOD1 0 0 1 CH2MOD0 0 1 0 FM AM NICAM CHANNEL 2 7.3.6.1 Notes It is recommended to switch the FM sound mode identification off whenever the received program is not a terrestrial 2-carrier sound. Switching the identification off will reset the associated hardware to a defined state. 1998 Apr 27 23 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder TDA9874H Changing the FM identification mode during FM reception may cause a brief flickering of bit IDSTE or IDDUA in the Device Status Register (see Section 7.4.1). When Channel 2 is used to receive FM sound carriers with the current application proposal (see Chapter 9), it is recommended to set the TIMPOL bit HIGH (write subaddress 14; see Section 7.3.11) for best S/N performance. 7.3.7 FM DE-EMPHASIS REGISTER (FMDR) This register is used to select the proper de-emphasis characteristics as appropriate for the standard of the received carrier. Bits B3 to B0 apply to sound carrier 1, bits B7 to B4 apply to sound carrier 2. In the event of A2 reception, both groups must be set to the same characteristics. The default setting at power-up is 10001000. Table 26 FM De-emphasis Register (subaddress 10) 7 ADEEM2 6 FMDSC23 5 FMDSC22 4 FMDSC21 3 ADEEM1 2 FMDSC13 1 FMDSC12 0 FMDSC11 Table 27 Description of FMDR bits BIT 7 SYMBOL ADEEM2 DESCRIPTION Adaptive de-emphasis on/off. ADEEM2 = 1, activates the adaptive de-emphasis function (for Wegener-Panda 1 encoded programs), which is required for certain satellite FM channels. The standard FM de-emphasis must then be set to 75 s. ADEEM2 = 0, the adaptive de-emphasis is off. FM de-emphasis. The state of these 3 bits determine the FM de-emphasis for sound carrier 2; see Table 28. 6 5 4 3 FMDSC23 FMDSC22 FMDSC21 ADEEM1 Adaptive de-emphasis on/off. ADEEM1 = 1, activates the adaptive de-emphasis function (for Wegener-Panda 1 encoded programs), which is required for certain satellite FM channels. The standard FM de-emphasis must then be set to 75 s. ADEEM1 = 0, the adaptive de-emphasis is off. FM de-emphasis. The state of these 3 bits determine the FM de-emphasis for sound carrier 1; see Table 28. 2 1 0 FMDSC13 FMDSC12 FMDSC11 Table 28 De-emphasis FMDSC23 FMDSC13 0 0 0 0 1 Note 1. The FM de-emphasis gain is 0 dB at 40 Hz. FMDSC22 FMDSC12 0 0 1 1 0 FMDSC21 FMDSC11 0 1 0 1 0 50 s 60 s 75 s J17 off DE-EMPHASIS(1) 1998 Apr 27 24 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.8 FM DEMATRIX REGISTER (FMMR) TDA9874H This register is used to select the proper dematrixing characteristics as appropriate for the standard of the received carrier and the related sound mode identification. For the dematrixing, it is assumed that the output from sound carrier 1 is on channel L input. Bits B3 to B7 are not used and should be set to logic 0. The default setting at power-up is 00000000. Table 29 FM Dematrix Register (subaddress 11) 7 - 6 - 5 - 4 - 3 - 2 FDMS2 1 FDMS1 0 FDMS0 Table 30 Description of FMMR bits BIT 7 6 5 4 3 2 1 0 SYMBOL - - - - - FDMS2 FDMS1 FDMS0 Dematrixing characteristics select. The state of these 3 bits select the dematrixing characteristics; see Table 31. DESCRIPTION These 5 bits are not used and should be set to logic 0. Table 31 Selection of the dematrixing characteristics FDMS2 0 0 0 0 1 1 FDMS1 0 0 1 1 0 0 FDMS0 0 1 0 1 0 1 L OUTPUT L input R input L input R input 2L input - R input L input + R input -----------------------------------------2 R OUTPUT L input R input R input L input R input L input - R input -----------------------------------------2 mono 2 dual dual swapped stereo Europe stereo Korea MODE forced mono 1998 Apr 27 25 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.9 CHANNEL 1 OUTPUT LEVEL ADJUST REGISTER (C1OLAR) TDA9874H This register is used to correct for standard and station-dependent differences of signal levels. Table 32 applies to sound carrier 1. The default setting at power-up is 00000000. Table 32 Channel 1 Output Level Adjust Register (subaddress 12) 7 B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 2 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 not defined -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 1998 Apr 27 26 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.10 CHANNEL 2 OUTPUT LEVEL ADJUST REGISTER (C2OLAR) TDA9874H This register is used to correct for standard and station-dependent differences of signal levels. Table 33 applies to sound carrier 2 in its FM and AM modes. In the event of FM stereo or FM dual language reception, Channels 1 and 2 shall be adjusted to the same level. The default setting at power-up is 00000000. Table 33 Channel 2 Output Level Adjust Register (subaddress 13) 7 B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 2 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 not defined -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 1998 Apr 27 27 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.11 NICAM CONFIGURATION REGISTER (NCONR) TDA9874H The default setting at power-up is 00000000. Table 34 NICAM Configuration Register (subaddress 14) 7 - 6 - 5 TIMPOL 4 DOUTEN 3 - 2 AMSEL 1 NDEEM 0 AMUTE Table 35 Description of NCONR bits BIT 7 6 5 SYMBOL - - TIMPOL Timing loop polarity. TIMPOL = 1, inverts the polarity. This feature can be used to compensate for the phase shift that is introduced by an external inverting amplifier at the pin Vtune. Such an amplifier could be used to provide a larger tuning voltage swing for the VCXO. TIMPOL = 0, sets the NICAM timing loop to normal polarity. Data output enable. DOUTEN = 1, enables the output of the NICAM serial data stream from the DQPSK demodulator and of the associated clock, PCLK. DOUTEN = 0, both outputs will be 3-stated. This bit is not used and should be set to logic 0. Auto-mute select. AMSEL = 1, the auto-mute will switch between NICAM sound and the analog mono input. This bit has only an effect when the auto-mute function is enabled and when the DAC has been selected in the Analog Output Select Register (see Section 7.3.17). AMSEL = 0, the auto-mute will switch between NICAM sound and the sound on the first sound carrier (i.e. FM mono or AM). De-emphasis on/off. NDEEM = 1, switches the NICAM J17 de-emphasis off. NDEEM = 0, switches the NICAM J17 de-emphasis on. Auto-muting on/off. AMUTE = 1, automatic muting is disabled. This bit has only an effect, when the second sound carrier is set to NICAM. AMUTE = 0, enables the automatic switching between NICAM and the program on the first sound carrier (i.e. FM mono or AM), dependent on the NICAM bit error rate. DESCRIPTION These 2 bits are not used and should be set to logic 0. 4 DOUTEN 3 2 - AMSEL 1 0 NDEEM AMUTE 7.3.11.1 Notes The decision of whether auto-muting is permitted shall be taken by the controlling microprocessor based on information contained in the TDA9874H's status registers. Thus, it depends on the strategy implemented in the software whether the auto-mute function is in accordance with "NICAM 728 ETS Revised for Data Applications" or any other preference. The NICAM de-emphasis gain is 0 dB at 40 Hz. The AMSEL bit has only an effect on the analog sound outputs (OUTL and OUTR). With regard to the digital sound output (I2S), the auto-mute will only switch between NICAM and the first sound carrier. When carrier 2 is in FM mode, the TIMPOL bit should be set HIGH, to achieve the best S/N performance with the current oscillator application proposal (see Chapter 9). 1998 Apr 27 28 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.12 NICAM OUTPUT LEVEL ADJUST REGISTER (NOLAR) TDA9874H This register is used to correct for standard and station-dependent differences of signal levels. Table 36 applies to both NICAM sound outputs. The default setting at power-up is 00000000. Table 36 NICAM Output Level Adjust Register (subaddress 15) 7 B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 2 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 not defined -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 1998 Apr 27 29 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.13 NICAM LOWER ERROR LIMIT REGISTER (NLELR) 7.3.16 TDA9874H DAC OUTPUT SELECT REGISTER (DACOSR) When the auto-mute function is enabled (see Section 7.3.11) and the NICAM bit error count is lower than the value contained in this register, the NICAM signal is selected (again) for reproduction. See also Section 7.3.14. The default setting at power-up is 00010100. Table 37 NICAM Lower Error Limit Register (subaddress 16) 7 B7 7.3.14 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 This register is used to define the signal source to be entered into the DAC. The DAC is used for signal output from digital sources at analog outputs. The two combinations of FM and NICAM shown in Table 42 apply to the (rare) condition that three different languages are being broadcast in an FM + NICAM system. They allow for a two-out-of-three selection for special applications. Note that the controlling microprocessor has to assure that the FM dematrix is set to the mono position. Some extra gain can be introduced at the input to the DAC to provide a coarse level adjust function. The default setting at power-up is 00000000. NICAM UPPER ERROR LIMIT REGISTER (NUELR) When the auto-mute function is enabled (see Section 7.3.11) and the NICAM bit error count is higher than the value contained in this register, the signal of the first sound carrier (i.e. FM mono or AM sound) or the analog mono input is selected for reproduction. The difference between upper and lower error limit constitutes a hysteresis to avoid frequent switching between NICAM and the program on the first sound carrier. The default setting at power-up is 01010000. Bits B2, B4, B5 and B6 are not used and should be set to logic 0. Table 40 DAC Output Select Register (subaddress 19) 7 DGS1 6 - 5 - 4 - 3 DGS0 2 - 1 0 DOS1 DOS0 Table 41 Selection of DAC gain DGS1 DGS0 0 0 1 0 1 DAC GAIN (dB) 0 3 6 9 Table 38 NICAM Upper Error Limit Register (subaddress 17) 7 B7 7.3.15 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 0 1 1 Table 42 Signal source left and right AUDIO MUTE CONTROL REGISTER (AMCONR) DOS1 DOS0 LEFT 0 0 1 1 Table 39 Audio Mute Control Register (subaddress 18) 7 - 6 MUTI2S 5 - 4 - 3 - 2 MUTOUT 1 - 0 - 0 1 0 1 FM/AM NICAM left FM/AM FM/AM RIGHT FM/AM NICAM right NICAM M1 NICAM M2 SIGNAL SOURCE Only bits 6 and 2 are used. The state of the unused bits should be set to logic 1. When any of these bits is set HIGH, the corresponding pair of output channels will be muted. A LOW bit allows normal signal output. The default setting at power-up is 11111111. 1998 Apr 27 30 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.17 ANALOG OUTPUT SELECT REGISTER (AOSR) TDA9874H This register is used to define both the signal source to be output at the analog outputs and the output channel selector mode. The DAC outputs are automatically muted, in case one of the analog inputs is selected for output. L+R The ------------- position of the matrix applies only to the DAC outputs, it is not available for analog input signals. 2 The default setting at power-up is 00000000. Table 43 Analog Output Select Register (subaddress 20) 7 - 6 CSM2 5 CSM1 4 CSM0 3 - 2 - 1 SS1 0 SS0 Table 44 Description of AOSR bits BIT 7 6 5 4 3 2 1 0 SYMBOL - CSM2 CSM1 CSM0 - - SS1 SS0 Signal source. These 2 bits select the signal source; see Table 46. These 2 bits are not used and should be set to logic 0. DESCRIPTION This bit is not used and should be set to logic 0. Output channel selection mode. These 3 bits select the output channel selection mode; see Table 45. Table 45 Output channel selection mode CSM2 0 0 0 0 1 CSM1 0 0 1 1 0 CSM0 0 1 0 1 0 L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2 Table 46 Signal source selection SS1 0 1 1 SS0 0 0 1 DAC external input mono input SIGNAL SOURCE 1998 Apr 27 31 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.18 DIGITAL AUDIO INTERFACE CONFIGURATION REGISTER (DAICONR) TDA9874H The default setting at power-up is 00000000. Table 47 Digital Audio Interface Configuration Register (subaddress 21) 7 - 6 - 5 - 4 SYSCL1 3 SYSCL0 2 SYSOUT 1 I2SFORM 0 I2SOUT Table 48 Description of DAICONR bits BIT 7 6 5 4 3 2 - - - SYSCL1 SYSCL0 SYSOUT System clock frequency select. These 2 bits select the frequency of the system clock; see Table 49. System clock output on/off. SYSOUT = 1, enables the output of a system (or master) clock signal at pin SYSCLK. SYSOUT = 0, the output will be off, thereby improving EMC performance. Serial output format. I2SFORM = 1, selects an MSB-aligned, MSB-first output format, i.e. a level change at the word select pin indicates the beginning of a new audio sample. I2SFORM = 0, selects the standard I2S output format. I2S output on/off. I2SOUT = 1, enables the output of serial audio data (2 pins) plus serial bit clock and word select in a format determined by the I2SFORM bit. The TDA9874H then is an I2S-bus master. I2SOUT = 0, the outputs mentioned will be 3-stated, thereby improving EMC performance. SYMBOL DESCRIPTION These 3 bits are not used and should be set to logic 0. 1 I2SFORM 0 I2SOUT Table 49 System clock frequency select SYSCL1 0 0 1 1 SYSCL0 0 1 0 1 SYSCLK OUTPUT 256fs 384fs 512fs 768fs FREQUENCY (MHz) 8.192 12.288 16.384 24.576 1998 Apr 27 32 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.19 I2S OUTPUT SELECT REGISTER (I2SOSR) TDA9874H This register is used to define both the signal source to be output at the I2S port and the mode of the digital matrix for signal selection. The two combinations of FM and NICAM shown in Table 53 apply to the (rare) condition that three different languages are being broadcast in an FM + NICAM system. They allow for a two-out-of-three selection for special applications. Note that the controlling microprocessor has to assure that the FM dematrix is set to the mono position. The default setting at power-up is 00000000. Table 50 I2S Output Select Register (subaddress 22) 7 - 6 ICSM2 5 ICSM1 4 ICSM0 3 - 2 - 1 ISS1 0 ISS0 Table 51 Description of I2SOSR bits BIT 7 6 5 4 3 2 1 0 SYMBOL - ICSM2 ICSM1 ICSM0 - - ISS1 ISS0 Signal source. These 2 bits select the signal source; see Table 53. These 2 bits are not used and should be set to logic 0. DESCRIPTION This bit is not used and should be set to logic 0. Output channel selection mode. These 3 bits select the output channel selection mode; see Table 52. Table 52 Mode of the digital matrix for signal selection ICSM2 0 0 0 0 1 ICSM1 0 0 1 1 0 ICSM0 0 1 0 1 0 L OUTPUT L input L input R input R input L+R ------------2 R OUTPUT R input L input R input L input L+R ------------2 Table 53 Signal source left and right SIGNAL SOURCE ISS1 0 0 1 1 ISS0 LEFT 0 1 0 1 FM left NICAM left FM mono FM mono RIGHT FM right NICAM right NICAM M1 NICAM M2 1998 Apr 27 33 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.3.20 I2S OUTPUT LEVEL ADJUST REGISTER (I2SOLAR) TDA9874H This register is used to adjust the output level at the I2S port. Left and right signal channels are treated identically. The default setting at power-up is 00000000. Table 54 I2S output Level Adjust Register (subaddress 23) 7 B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 2 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 not defined -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 1998 Apr 27 34 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.4 Slave transmitter mode TDA9874H As a slave transmitter, the TDA9874H provides 12 registers with status information and data, a part of which is for Philips internal purposes only. Each register is accessed by means of a subaddress. Detailed descriptions of the slave transmitter registers are given in Sections 7.4.1 to 7.4.9. Table 55 General format for reading data from the TDA9874H S SLAVE ADDRESS 0 A SUBADDRESS A Sr SLAVE ADDRESS 1 A DATA NAm P Table 56 Explanation of Tables 55 and 57 BIT S SLAVE ADDRESS 0 A SUBADDRESS Sr 1 DATA NAm Am P START condition 7-bit device address data direction bit (write to device) acknowledge (by the slave) address of register to read from repeated START condition data direction bit (read from device) data byte read from register not acknowledge (by the master) acknowledge (by the master) STOP condition FUNCTION Reading of data can start at any valid subaddress. It is allowed to read more than 1 data byte per transmission from the TDA9874H. In that case, the subaddress is automatically incremented after each data byte, resulting in reading the sequence of data bytes from successive register locations, starting at SUBADDRESS. Table 57 Format of a transmission using automatic incrementing of subaddresses S SLAVE ADDRESS 0 A SUBADDRESS A Sr SLAVE ADDRESS 1 A DATA BYTE Am DATA NAm P n data bytes with auto-increment of subaddresses Each data byte in a read sequence, except for the last one, is acknowledged with Am. The subaddresses `wrap around' from decimal 255 to 0. If an attempt is made to read from a non-existing subaddress, the device will send a data pattern of all ones, i.e. FF in hexadecimal notation. 1998 Apr 27 35 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Apr 27 36 Philips Semiconductors Table 58 Overview of the slave transmitter registers Digital TV sound demodulator/decoder SUBADDRESS (DECIMAL) 0 1 2 3 4 5 6 7 252(2) 253(2) 254(2) 255(2) Notes DATA FUNCTION 7 P2IN C4 B7 AD7 OVW B7 B7 -(1) B7 B7 B7 B7 6 P1IN C3 B6 AD6 SAD B6 B6 -(1) B6 B6 B6 B6 5 RSSF C2 B5 AD5 -(1) B5 B5 -(1) B5 B5 B5 B5 4 AMSTAT C1 B4 AD4 CI1 B4 B4 B4 B4 B4 B4 B4 3 VDSP OSB B3 AD3 CI2 B3 B3 B3 B3 B3 B3 B3 2 IDDUA CFC B2 AD2 AD10 B2 B2 B2 B2 B2 B2 B2 1 IDSTE S/MB B1 AD1 AD9 B1 B1 B1 B1 B1 B1 B1 0 -(1) D/SB B0 AD0 AD8 B0 B0 B0 B0 B0 B0 B0 device status (identification, etc.) NICAM status NICAM error count additional data (LSB) additional data (MSB) level read-out (MSB) level read-out (LSB) SIF level Test Register 2 Test Register 1 device identification code software identification code 1. Value is undefined. 2. Registers from subaddress 252 to 255 are for Philips internal purposes only. They are considered as a set of registers for the identification of individual members and some key parameters in a family of devices. Preliminary specification TDA9874H Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.4.1 DEVICE STATUS REGISTER (DSR) TDA9874H Table 59 Device Status Register (subaddress 0) 7 P2IN 6 P1IN 5 RSSF 4 AMSTAT 3 VDSP 2 IDDUA 1 IDSTE 0 - Table 60 Description of DSR bits BIT 7 SYMBOL P2IN DESCRIPTION Input from Port 2. This bit reflects the status of the P2 general purpose port pin; see Section 7.3.2. If P2IN = 1, then the P2 general purpose port pin is HIGH. If P2IN = 0, then the P2 general purpose port pin is LOW. Input from Port 1. This bit reflects the status of the P1 general purpose port pin; see Section 7.3.2. If P1IN = 1, then the P1 general purpose port pin is HIGH. If P1IN = 0, then the P1 general purpose port pin is LOW. Reserve Sound Switching Flag. RSSF = 1, this bit is a copy of the C4 bit in the NICAM Status Register (see Section 7.4.2). It indicates that the FM (or AM for standard L) sound matches the digital transmission and auto-muting should be enabled. RSSF = 0, auto-muting should be disabled, as analog and digital sound are different. Auto-mute Status. If this bit is HIGH, it indicates that the auto-muting function has switched from NICAM to the program of the first sound carrier (i.e. FM mono or AM in NICAM L systems). Identification of NICAM sound. VDSP = 1, indicates that digital transmission is a sound source. VDSP = 0, indicates the transmission is either data or a currently undefined format. Identification of FM dual sound; A2 systems. If IDDUA = 1, an FM dual-language signal has been identified. When neither IDSTE nor IDDUA = 1, the received signal is assumed to be FM mono (A2 systems only). Identification of FM stereo; A2 systems. If IDSTE = 1, an FM stereo signal has been identified (A2 systems only). Value is undefined. 6 P1IN 5 RSSF 4 AMSTAT 3 VDSP 2 IDDUA 1 0 IDSTE - 1998 Apr 27 37 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.4.2 NICAM STATUS REGISTER (NISR) TDA9874H Table 61 NICAM Status Register (subaddress 1) 7 C4 6 C3 5 C2 4 C1 3 OSB 2 CFC 1 S/MB 0 D/SB Table 62 Description of NISR bits BIT 7 6 5 4 3 SYMBOL C4 C3 C2 C1 OSB Synchronization bit. OSB = 1, indicates that the device has both frame and C0 (16 frame) synchronization. OSB = 0, indicates the audio output from the NICAM part is digital silence. Configuration change. CFC = 1, indicates a configuration change at the 16 frame (C0) boundary. Identification of NICAM stereo. S/MB = 1, indicates stereo mode. Identification of NICAM dual mono. D/SB = 1, indicates dual mono mode. DESCRIPTION NICAM application control bits. These bits correspond to the control bits C1 to C4 in the NICAM transmission. 2 1 0 CFC S/MB D/SB 7.4.2.1 Notes The TDA9874H does not support the extended control modes. Therefore, the program of the first sound carrier (i.e. FM mono or AM) is selected for reproduction in case bit C3 is set HIGH, independent of bit AMUTE in the NICAM Configuration Register being set or not. When a NICAM transmitter is switched off, the device will lose synchronization. In that case the program of the first sound carrier is selected for reproduction, independent of bit AMUTE being set or not. 7.4.3 NICAM ERROR COUNT REGISTER (NIECR) Bits B7 to B0 contain the number of errors occurring in the previous 128 ms period. The register is updated every 128 ms. Table 63 NICAM Error Count Register (subaddress 2) 7 B7 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 1998 Apr 27 38 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.4.4 DATA REGISTERS (DR1 AND DR2) TDA9874H The contents of these two registers provide information on the additional data bits. ADBYTE0 is stored at subaddress 3. Table 64 Data Register 1 (subaddress 3) 7 AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 0 AD0 Table 65 Description of DR1 bits BIT 7 to 0 SYMBOL AD7 to AD0 DESCRIPTION The lower 8 bits of the additional data word. Table 66 Data Register 2 (subaddress 4) 7 OVW 6 SAD 5 - 4 CI1 3 CI2 2 AD10 1 AD9 0 AD8 Table 67 Description of DR2 bits BIT 7 6 5 4 3 2 1 0 SYMBOL OVW SAD - CI1 CI2 AD10 AD9 AD8 DESCRIPTION If this bit is HIGH, new additional data bits are written to the IC without the previous bits being read. When SAD = 1, new additional data is written into the IC. This bit is reset, when the additional data bits are read. Value is undefined. These 2 bits are CI bits decoded by majority logic from the parity checks of the last ten samples in a frame. The upper 3 bits of the additional data word. 1998 Apr 27 39 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 7.4.5 LEVEL READ-OUT REGISTERS (LRRA AND LRRB) TDA9874H Table 71 Test Register 2 (subaddress 252) 7 B7 7.4.8 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 These two bytes constitute a word that provides data from a location that has been specified with the FM Monitor Select Register (see Section 7.3.3). The most significant byte of the data is stored at subaddress 5. Table 68 Level Read-out Register A (subaddress 5) 7 B7(1) Note 1. B7 is the most significant bit or sign bit of the word. Table 69 Level Read-out Register B (subaddress 6) 7 B7 Note 1. B0 is the least significant bit of the word. 7.4.6 SIF LEVEL REGISTER (SIFLR) 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0(1) 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 TEST REGISTER 1 (TR1) This register contains as a binary number the highest subaddress used for slave transmitter (status) registers. The first version will have the identification 00101111. Table 72 Test Register 1 (subaddress 253) 7 B7 7.4.9 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 DEVICE IDENTIFICATION CODE (DIC) There will be several devices in the digital TV sound processor family, with TDA9874H being the second member. This byte is used to identify the individual family members. The first version will have the identification 00000111. Table 73 Device Identification Code (subaddress 254) 7 B7 7.4.10 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 When the SIF AGC is on, bits B4 to B0 of this register contain a number that gives an indication of the SIF input level. That number can be interpreted in the same way as the AGC Gain Register setting (see Section 7.3.1), i.e. if the SIF AGC were set to a fixed gain and the same number loaded into the AGC Gain Register, the current SIF input signal level would generate an SIF ADC output close to full-scale. When the SIF AGC is off, this register returns the contents of the AGC Gain Register. Bits B5 to B7 are not used and are undefined. Table 70 SIF Level Register (subaddress 7) 7 -(1) Note 1. Value is undefined. 7.4.7 TEST REGISTER 2 (TR2) 6 -(1) 5 -(1) 4 B4 3 B3 2 B2 1 B1 0 B0 SOFTWARE IDENTIFICATION CODE (SIC) It is likely that during the life time of this family of devices several versions of the DSP software will be made, e.g. to take care of new application concepts, respond to customer wishes, etc. This byte is used to identify the different releases. The first version will have the identification 00000111. Table 74 Software Identification Code (subaddress 255) 7 B7 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 This register contains as a binary number the highest subaddress used for slave receiver registers. The first version will have the identification 00101111. 1998 Apr 27 40 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 8 I2S-BUS DESCRIPTION TDA9874H other ICs. If output is desired, it has to be activated by means of an I2C-bus command. When output is enabled, serial audio data can be taken from pin SDO. Depending on the signal source, switch and matrix positions, the output can be either mono, stereo or dual language. The Word Select output (WS) is clocked with the audio sample frequency of 32 kHz. The Serial Clock output (SCK) is clocked at a frequency of 2.048 MHz. This means, that there are 64 clock pulses per pair of stereo output samples, or 32 clock pulses per sample. There are 18 significant bits used on the Serial Data Output (SDO). A symmetrical system clock output (SYSCLK) is available from the TDA9874H as a master clock for external digital audio devices. At power-up, the clock is off. It can be enabled and the output frequency set via an I2C-bus command. Available output frequencies are 8.192 MHz, 12.288 MHz, 16.384 MHz and 24.576 MHz. The digital audio interface of the TDA9874H consists of a serial audio output and associated clock signals. It can be used to supply digital audio signals from received TV programs to a suitable output device, e.g. a DAC or an AES/EBU transmitter. Two serial audio formats are supported at the digital audio interface, i.e. the I2S-bus format and a very similar MSB-aligned format. The difference is explained in Fig.6. In both formats the left audio channel of a stereo sample pair is output first, and is on the Serial Data line (SDO) when the Word Select line (WS) is LOW. Data is written with the trailing edge of SCK and read with the leading edge of SCK. The most significant bit is sent first. At power-up, the outputs of the digital audio interface are 3-stated to reduce EMC and allow for combinations with handbook, full pagewidth SCK WS SDO LSB MSB LSB MSB MGK759 one sample a. MSB-aligned format. handbook, full pagewidth SCK WS SDO LSB MSB LSB MSB MGK758 one sample b. I2S-bus format. Fig.6 Serial audio interface formats. 1998 Apr 27 41 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 9 EXTERNAL COMPONENTS +5 V 470 nF 10 47 F VDDA3 VSSA3 EXTIL Vref2 P2 470 nF 470 nF MONOIN 470 nF VSSD4 external input +5 V 3.3 TDA9874H handbook, full pagewidth 470 nF Lx(2) 2.2 F audio output 10 nF 44 OUTL 1 43 42 41 40 39 38 37 36 35 34 33 SCK 2.2 F SYSCLK WS OUTR 10 nF VDDA1 470 nF V SSA1 VDDD4 EXTIR P1 2 32 I2S-bus +5 V 10 3 31 SDO 4 30 SDA I2C-bus VSSD1 470 nF Lx(2) VSSD2 5 29 SCL +5 V 10 VDDD1 6 TDA9874H 28 VDDD3 Lx(2) 10 470 nF +5 V 7 3.3 470 nF Lx(2) TP2 (1) 27 VSSD3 1 F +5 V VDDD2 8 26 CRESET SIF1 9 25 Vref1 47 pF NICAM 10 24 100 nF TP1 (1) SIF2 11 12 PCLK 13 ADDR1 14 Vtune 15 XTALI 16 XTALO 17 TEST2 18 Iref 19 ADDR2 20 VSSA2 21 VDDA2 22 TEST1 23 47 pF 33 pF optional oscillator circuitry 33 pF 14 Vtune 15 XTALI 16 XTALO 10 k 24.576 MHz (1) 470 nF 8.2 k 10 +5 V (1) MGK757 33 pF 24.568 MHz 10 k 33 pF 39 k 330 nF 33 nF 3.3 H 39 k BB135 39 k 330 nF HVU350 33 nF All analog and digital supply ground pins are connected internally. (1) TP1, TP2, TEST1 and TEST2 should be connected to VSS during normal operation. (2) Lx: ferrite bead, e.g. BLM 31A601S (Murata). Fig.7 External components. 1998 Apr 27 42 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VDD IIK IOK Io DC supply voltage voltage differences between two VDD pins DC input clamp diode current DC output clamp diode current output type 4 mA DC output source or sink current output type 4 mA Vi < -0.5 V or Vi > VDD + 0.5 V Vo < -0.5 V or Vo > VDD + 0.5 V PARAMETER CONDITIONS TDA9874H MIN. MAX. UNIT -0.5 - - - +6.5 550 10 20 20 62 28 - 100 0.9 +125 +70 - V mV mA mA mA mA mA mA mW W C C V V -0.5 V < Vo < VDD + 0.5 V - - - 100 - - -55 -20 note 1 note 2 200 IDDD, ISSD DC VDDD or VSSD current per digital supply pin IDDA, ISSA DC VDDA or VSSA current per analog supply pin Ilu(prot) P Ptot Tstg Tamb Ves latch-up protection current power dissipation per output total power dissipation storage temperature operating ambient temperature electrostatic handling 2000 - Notes 1. Human body model: C = 100 pF; R = 1.5 k. 2. Machine model: C = 200 pF; L = 0.75 H; R = 0 . 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 70 UNIT K/W 1998 Apr 27 43 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder TDA9874H 12 CHARACTERISTICS VDD = 5 V; Tamb = 25 C; settings in accordance with B/G standard; FM deviation 50 kHz; fmod = 1 kHz; FM sound parameters in accordance with system A2; NICAM in accordance with "EBU specification"; 1 k measurement source resistance for AF inputs; VSIF = 300 mV (peak-to-peak); AGCOFF = 0; AGCSLOW = 1; level and gain settings according to note 2 with external components of Fig.7; unless otherwise specified. SYMBOL Digital supplies VDDD1 VSSD1 IDDD1 VDDD2 VSSD2 IDDD2 VDDD3 VSSD3 IDDD3 digital supply voltage 1 digital ground supply 1 digital supply current 1 digital supply voltage 2 digital ground supply 2 digital supply current 2 digital supply voltage 3 digital ground supply 3 digital supply current 3 VDDD3 = 5.5 V VDDD3 = 5.0 V Demodulator supplies and references VDDA2 VSSA2 IDDA2 VDDD4 VSSD4 IDDD4 Vref1 Iref(sink) VDDA3 VSSA3 IDDA3 VDDA1 analog supply voltage 2, demodulator part analog ground supply 2, demodulator part analog supply current 2, demodulator part digital supply voltage 4 digital ground supply 4 digital supply current 4 analog reference voltage 1, demodulator part Vref1 sink current analog supply voltage 3, operational amplifiers analog ground supply 3, operational amplifiers analog supply current 3, operational amplifiers analog supply voltage 1, audio DAC part VDDA = 5.5 V VDDA = 5.0 V VDDD2 = 5.5 V VDDD2 = 5.0 V with respect to VDDA2/VSSA2 VDDA = 5.5 V VDDA = 5.0 V 4.5 - 20 17 4.5 - 40 34 35 170 5.0 0.0 24 21.5 5.0 0.0 50 44 50 220 5.5 - 28 25 5.5 - 60 54 65 260 V V mA mA V V mA mA % A VDDD2 = 5.5 V VDDD2 = 5.0 V VDDD1 = 5.5 V VDDD1 = 5.0 V 4.5 - 8 7 4.5 - 25 22 4.5 - 7 6 5.0 0.0 12 10 5.0 0.0 32 28 5.0 0.0 12 11 5.5 - 16 14 5.5 - 37 33 5.5 - 16 15 V V mA mA V V mA mA V V mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Audio supplies and references 4.5 - 1.3 1.2 4.5 5.0 0.0 1.8 1.7 5.0 5.5 - 2.4 2.3 5.5 V V mA mA V 1998 Apr 27 44 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder TDA9874H SYMBOL VSSA1 IDDA1 Vref2 PARAMETER analog ground supply 1, audio DAC part analog supply current 1, audio DAC part reference voltage 2, audio DACs and operational amplifiers CONDITIONS MIN. - TYP. 0.0 2.1 1.9 50 MAX. - 3.1 2.8 - UNIT V mA mA % VDDA = 5.5 V; digital silence VDDA = 5.0 V; digital silence with respect to VDDA3/VSSA3 1.2 1.1 - Z(Vref2-VDDA3) impedance Vref2 to VDDA3 Z(Vref2-VSSA3) impedance Vref2 to VSSA3 Digital inputs and outputs INPUTS - - 20 20 - - k k CMOS level input, high drive, pull-down (TEST1, TEST2, TP1 and TP2) VIL VIH Ci Zi VIL VIH Vhys Ci Zi LOW-level input voltage HIGH-level input voltage input capacitance input impedance - 3.0 - - - 4.0 - - - - - - 50 - - - 50 1.6 - 10 - 1.0 - 10 - V V pF k CMOS level input, hysteresis, high drive, pull-up (CRESET) LOW-level input voltage HIGH-level input voltage hysteresis voltage input capacitance input impedance V V V pF k 0.33VDDD - INPUTS/OUTPUTS I2C level input with Schmitt trigger, open-drain output stage (SCL and SDA) VIL VIH Vhys ILI Ci VOL CL LOW-level input voltage HIGH-level input voltage hysteresis voltage input leakage current input capacitance LOW-level output voltage load capacitance active pull-up passive pull-up - 3.0 - - - - - - - - - - - - - 1.6 - 10 10 0.5 400 200 V V V A pF V pF pF 0.33VDDD - TTL/CMOS level, high drive, 4 mA 3-state output stage, pull-up (PCLK, NICAM, ADDR1, ADDR2, P1, P2, SCK, WS and SDO) VIL VIH Ci VOL VOH CL 1998 Apr 27 LOW-level input voltage HIGH-level input voltage input capacitance LOW-level output voltage HIGH-level output voltage load capacitance IOL = +3 mA IOH = -3 mA active pull-up 45 - 2.0 - - 2.9 - - - - - - - 0.8 - 10 0.5 - 50 V V pF V V pF Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder TDA9874H SYMBOL Zi OUTPUTS PARAMETER input impedance CONDITIONS MIN. - TYP. 50 MAX. - UNIT k 4 mA 3-state output stage (SYSCLK) VOL VOH CL ILIZ VSIF(p-p) fi Ri Ci fFM fFM(FS) C/NFM LOW-level output voltage HIGH-level output voltage load capacitance 3-state leakage current Vi = 0 to VDDD note 5 IOL = +2 mA IOH = -2 mA - 2.9 - - - - - - - - 13 7.5 - - 77 0.5 - 50 10 V V pF A SIF1 and SIF2 analog inputs composite SIF input voltage range (peak-to-peak value) input frequency input resistance input capacitance FM deviation FM deviation full-scale level FM carrier C/Nc ratio B/G standard; THD < 1% NFM bandwidth = 6 MHz; white noise for S/N = 40 dB; "CCIR468-2"; quasi peak Nc bandwidth = 6 MHz; bit error rate = 10-3; white noise 60 4 10 - 100 - terrestrial FM; level adjust 0 dB 150 700 9.2 16 11 - - - mV MHz k pF kHz kHz dB FM ------------Hz dB N ---------Hz C/NN NICAM carrier C/Nc ratio - 66 - Demodulator performance Vo(nom)(RMS) THD + N nominal level output voltage (RMS value) note 2 400 - 500 0.3 600 0.5 mV % total harmonic distortion + noise from FM source to any output with low-pass 30 kHz/3 dB; Vo = 1 V (RMS) from NICAM source to any output with low-pass 30 kHz/3 dB; Vo = 1 V (RMS) - 0.1 0.3 % S/N signal-to-noise ratio SC1 from FM source to any output; Vo = 1 V (RMS); "CCIR468-2"; quasi peak; TIMPOL bit HIGH SC2 from FM source to any output; Vo = 1 V (RMS); "CCIR468-2"; quasi peak; TIMPOL bit HIGH NICAM source; Vo = 1 V (RMS); "CCIR468-2"; quasi peak 61 65 - dB 57 60 - dB NICAM in accordance with "EBU specification"; note 1 1998 Apr 27 46 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder TDA9874H SYMBOL B(-3dB) PARAMETER -3 dB bandwidth CONDITIONS from FM source to any output from NICAM source to any output MIN. 14.5 14.5 -2 65 40 50 TYP. 15 15 - 70 45 - MAX. - - +1 - - - UNIT kHz kHz dB dB dB dB fresp cd(dual) cs(stereo) AM frequency response 20 Hz to 14 kHz dual signal channel separation stereo channel separation AM suppression for FM from FM/NICAM to any output; reference 1 kHz note 6 note 7 AM: 1 kHz, 30% modulation; reference: 1 kHz, 50 kHz deviation SIF level 100 mV (RMS); 54% AM; 1 kHz AF; "CCIR468"; quasi peak dmAM AM demodulation - 36 - dB IDENTIFICATION FOR FM SYSTEMS mpilot(ident) C/Npilot(ident) hys(tun) fident pilot modulation for identification pilot sideband C/N for identification start hysteresis identification window B/G stereo slow mode medium mode fast mode B/G dual slow mode medium mode fast mode ton(ident) total identification time on slow mode medium mode fast mode toff(ident) total identification time off slow mode medium mode fast mode Mono and external inputs Vi(nom)(rms) Vi(cl)(rms) Ri nominal level input voltage (RMS value) clipping level input voltage (RMS value) input resistance note 2 THD < 3%; note 3 note 3 - 1250 28 500 1400 35 - - 42 mV mV k 273.44 - 272.07 - 270.73 - - - - - - - - - - - - - 274.81 Hz 276.20 Hz 277.60 Hz 2 1 0.5 2 1 0.5 s s s s s s 116.85 - 116.11 - 114.65 - 118.12 Hz 118.89 Hz 120.46 Hz 25 - - 50 32 - 75 - 2 % dB -----Hz dB 1998 Apr 27 47 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder TDA9874H SYMBOL Analog audio outputs Vo(clip)(rms) Ro RL(AC) RL(DC) Co(L) Voffset(DC) mute Bline Gro PSRR PARAMETER CONDITIONS MIN. - TYP. MAX. - 375 - - 12 70 - - - - UNIT clipping level output voltage (RMS value) output resistance AC load resistor DC load resistor output load capacitor static DC offset voltage mute suppression bandwidth roll-off gain at 14.5 kHz power supply ripple rejection THD < 3% 1400 150 10 10 - - mV k k nF mV dB kHz dB dB 250 - - 10 30 - - -2 45 nominal input signal from any source; fi = 1 kHz; note 2 from external and mono source; -3 dB bandwidth from any source fripple = 70 Hz; Vripple = 100 mV (peak); CVref = 47 F; signal from I2S 80 20 -3 40 Audio performance THD + N total harmonic distortion + noise Vin/out = 1 V (RMS); fi = 1 kHz; bandwidth 20 Hz to 20 kHz; from external/mono input to output copy signal-to-noise ratio reference voltage V0 = 1.4 V (RMS); fi = 1 kHz; "CCIR468"; quasi peak; from external/mono input to output copy between any analog input pairs; fi = 1 kHz between left and right of external input pair between left and right of output pair VCXO and clock generation VCXO - 0.1 0.3 % S/N 78 90 - dB ct cs crosstalk attenuation channel separation 70 65 60 - - - - - - dB dB dB Crystal input Ci Vbias(DC) input capacitance DC bias voltage Ri = 100 k - 3.5 - 2.3 16.6 - 3.63 10 3.7 - 2.8 18.8 pF V Crystal output Vosc(p-p) Vbias(DC) Gm oscillation amplitude (peak-to-peak value) DC bias voltage mutual conductance at 24.576 MHz 48 1.4 2.53 17.6 V V mS 1998 Apr 27 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder TDA9874H SYMBOL Co fxtal CL C1 C0 S PARAMETER output capacitance CONDITIONS MIN. - - TYP. MAX. 10 - - - 7 - UNIT pF CRYSTAL SPECIFICATION (FUNDAMENTAL MODE) crystal frequency load capacitance series capacitance parallel capacitance pulling sensitivity CL changed from 18 to 16 pF note 4 - - - - - - 2RR -20 - across temperature range - - 24.576 20 20 - 25 - - +25 - - - MHz pF fF pF 10 ----------pF C 10-6 10-6 10 ----------year -6 -6 Rs(eq) Rs(eq)(UM) Tamb XJ XD XA equivalent series resistance equivalent series resistance of unwanted mode operating ambient temperature adjustment tolerance drift ageing at nominal frequency 30 - +70 30 30 5 Notes 1. Audio performance is limited by the dynamic range of the NICAM 728 system. Due to companding, the quantization noise is never lower than -62 dB with respect to the input level. 2. Definition of levels and level setting (see Tables 75 and 76): a) The full-scale level for analog audio signals is VFS = 1.4 V (RMS). The nominal level at the digital crossbar switch is defined at -15 dB (FS). b) Nominal audio input levels: extern, mono: 500 mV (RMS); -9 dB (FS). 3. If the supply voltage for the TDA9874H is switched off, because of the ESD protection circuitry all audio input pins are short-circuited. 4. The Philips crystal (order number 9922 520 20106) is suited for this application. 5. The demodulation/decoding is still functional above and below the limits given. 6. FM source; in dual mode only A (respectively B) signal modulated; measured at B (respectively A) channel output; Vo = 1 V (RMS) of modulated channel. 7. FM source; in stereo mode only L (respectively R) signal modulated; measured at R (respectively L) channel output; Vo = 1 V (RMS) of modulated channel. 1998 Apr 27 49 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Apr 27 50 Philips Semiconductors Table 75 Level setting FM, AM and NICAM 0 dB (FS) = 1.4 V (RMS), FS means full scale. SOURCE TRANSMITTER NOMINAL MODULATION DEPTH NOMINAL LEVEL AT DEMODULATOR OUTPUT -24 dB (FS) -19 dB (FS) LEVEL ADJUST SETTING +9 dB +4 dB NOMINAL LEVEL AT CROSSBAR -15 dB (FS) (spread of 0.5 dB due to different transmitter references) DAC GAIN SETTING +6 dB NOMINAL OUTPUT VOLTAGE VO 500 mV (RMS) Digital TV sound demodulator/decoder FM 15 kHz deviation M standard FM B/G, D/K, I standard AM L/L accent standard NICAM B/G, D/K, L standard NICAM I standard 27 kHZ deviation 54% -19 dB (FS) +4 dB -11.2 dB (FS) -18 dB (FS) +3 dB -15.8 dB (FS) -23 dB (FS) +8 dB Table 76 Level setting SAT FM 0 dB (FS) = 1.4 V (RMS), FS means full scale. SOURCE SAT FM stereo SAT FM mono TRANSMITTER MAXIMUM MODULATION DEPTH 50 kHz deviation 85 kHz deviation NOMINAL LEVEL AT DEMODULATOR OUTPUT -13 dB (FS) -9 dB (FS) LEVEL ADJUST SETTING +4 dB 0 dB MAXIMUM LEVEL AT CROSSBAR -9 dB (FS) DAC GAIN SETTING +6 dB MAXIMUM OUTPUT VOLTAGE VO 1 V (RMS) Preliminary specification TDA9874H Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 13 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm TDA9874H SOT205-1 c y X 33 34 23 22 ZE A e E HE wM bp pin 1 index 44 1 11 ZD bp D HD wM B vM B 12 detail X L Lp A A2 A1 (A 3) e vM A 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.60 A1 0.25 0.05 A2 2.3 2.1 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 14.1 13.9 E (1) 14.1 13.9 e 1 HD 19.2 18.2 HE 19.2 18.2 L 2.35 Lp 2.0 1.2 v 0.3 w 0.15 y 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT205-1 REFERENCES IEC 133E01A JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 1998 Apr 27 51 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 14 SOLDERING 14.1 Introduction 14.3 Wave soldering TDA9874H There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). 14.2 Reflow soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Repairing soldered joints Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 1998 Apr 27 52 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder 15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values TDA9874H This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 17 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 Apr 27 53 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder NOTES TDA9874H 1998 Apr 27 54 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder NOTES TDA9874H 1998 Apr 27 55 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998 SCA59 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545104/1200/01/pp56 Date of release: 1998 Apr 27 Document order number: 9397 750 02597 |
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